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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-21 14:14:44 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-21 14:14:44 +0000 |
| commit | 2213fba5c5c4ea85477b7c5985e10d2f17f027c6 (patch) | |
| tree | 3a038100bb0ad4d1bcb76696ad8e04eaff714385 /system | |
| parent | f2e2410a505ef48516f121ce1b2232ba7aa389af (diff) | |
| download | gem5-2213fba5c5c4ea85477b7c5985e10d2f17f027c6.tar.xz | |
arm: Blame the right instruction address on a Prefetch Abort
CPU models (e.g., O3CPU) issue instruction fetches for the whole cache
block rather than a specific instruction. Consequently the TLB lookups
translate the cache block virtual address. When the TLB lookup fails,
however, the Prefetch Abort must be raised for the PC of the
instruction that caused the fault rather than for the address of the
block.
This change fixes the way we instantiate the PrefetchAbort faults to
use the PC of the request rather the address of the instruction fetch
request.
Change-Id: I8e45549da1c3be55ad204a060029c95ce822a851
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'system')
0 files changed, 0 insertions, 0 deletions