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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:49 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:49 -0400 |
commit | 4de3205afaac1fd11876b33675aa6f49c9632764 (patch) | |
tree | ff510cdaafefa5f7e27bc0b21c6fbd447564a1d9 /tests/configs/base_config.py | |
parent | 597d2aa3a661587268e3d79cf4726212329fb4af (diff) | |
download | gem5-4de3205afaac1fd11876b33675aa6f49c9632764.tar.xz |
config: Add a BaseSESystem builder for re-use in regressions
This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).
The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.
Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.
Diffstat (limited to 'tests/configs/base_config.py')
-rw-r--r-- | tests/configs/base_config.py | 55 |
1 files changed, 51 insertions, 4 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index a4b3969ef..0cafacdda 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012 ARM Limited +# Copyright (c) 2012-2013 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -34,6 +34,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Andreas Sandberg +# Andreas Hansson from abc import ABCMeta, abstractmethod import m5 @@ -56,17 +57,19 @@ class BaseSystem(object): __metaclass__ = ABCMeta - def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU, - num_cpus=1, checker=False): - """Initialize a simple ARM system. + def __init__(self, mem_mode='timing', mem_class=SimpleMemory, + cpu_class=TimingSimpleCPU, num_cpus=1, checker=False): + """Initialize a simple base system. Keyword Arguments: mem_mode -- String describing the memory mode (timing or atomic) + mem_class -- Memory controller class to use cpu_class -- CPU class to use num_cpus -- Number of CPUs to instantiate checker -- Set to True to add checker CPUs """ self.mem_mode = mem_mode + self.mem_class = mem_class self.cpu_class = cpu_class self.num_cpus = num_cpus self.checker = checker @@ -153,6 +156,50 @@ class BaseSystem(object): defined by this class.""" pass +class BaseSESystem(BaseSystem): + """Basic syscall-emulation builder.""" + + def __init__(self, **kwargs): + BaseSystem.__init__(self, **kwargs) + + def init_system(self, system): + BaseSystem.init_system(self, system) + + def create_system(self): + system = System(physmem = self.mem_class(), + membus = CoherentBus(), + mem_mode = self.mem_mode) + system.system_port = system.membus.slave + system.physmem.port = system.membus.master + self.init_system(system) + return system + + def create_root(self): + system = self.create_system() + m5.ticks.setGlobalFrequency('1THz') + return Root(full_system=False, system=system) + +class BaseSESystemUniprocessor(BaseSESystem): + """Basic syscall-emulation builder for uniprocessor systems. + + Note: This class is only really needed to provide backwards + compatibility in existing test cases. + """ + + def __init__(self, **kwargs): + BaseSESystem.__init__(self, **kwargs) + + def create_caches_private(self, cpu): + # The atomic SE configurations do not use caches + if self.mem_mode == "timing": + # @todo We might want to revisit these rather enthusiastic L1 sizes + cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'), + L1Cache(size='256kB'), + L2Cache(size='2MB')) + + def create_caches_shared(self, system): + return None + class BaseFSSystem(BaseSystem): """Basic full system builder.""" |