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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:32 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:32 -0400 |
commit | 1f6d5f8f849f50a3646f586b1274708537124ef3 (patch) | |
tree | 03c98c46d500fbd9ac8135baea399813ea3d5644 /tests/configs/base_config.py | |
parent | 1884bcc03ba2b6e734b4bd379d8542596e6d5c84 (diff) | |
download | gem5-1f6d5f8f849f50a3646f586b1274708537124ef3.tar.xz |
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.
As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.
--HG--
rename : src/mem/Bus.py => src/mem/XBar.py
rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc
rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh
rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc
rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh
rename : src/mem/bus.cc => src/mem/xbar.cc
rename : src/mem/bus.hh => src/mem/xbar.hh
Diffstat (limited to 'tests/configs/base_config.py')
-rw-r--r-- | tests/configs/base_config.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index e9487546d..ccf1ea6f8 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -102,7 +102,7 @@ class BaseSystem(object): Returns: A bus that CPUs should use to connect to the shared cache. """ - system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain) + system.toL2Bus = CoherentXBar(clk_domain=system.cpu_clk_domain) system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master @@ -184,7 +184,7 @@ class BaseSESystem(BaseSystem): def create_system(self): system = System(physmem = self.mem_class(), - membus = CoherentBus(), + membus = CoherentXBar(), mem_mode = self.mem_mode) system.system_port = system.membus.slave system.physmem.port = system.membus.master |