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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-10-05 13:13:23 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-10-05 13:13:23 -0500 |
commit | 17dbb49294e06ce3c486648da899973100c633f1 (patch) | |
tree | f2c3938a7d08d3faf8b50bb5fa6c473cb3135675 /tests/configs/base_config.py | |
parent | d1811cc6cf7a57c7b52da7303e6bbb55d9fbe058 (diff) | |
download | gem5-17dbb49294e06ce3c486648da899973100c633f1.tar.xz |
tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
Diffstat (limited to 'tests/configs/base_config.py')
-rw-r--r-- | tests/configs/base_config.py | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index a3e1e0271..3f28ada5d 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -58,7 +58,8 @@ class BaseSystem(object): __metaclass__ = ABCMeta def __init__(self, mem_mode='timing', mem_class=SimpleMemory, - cpu_class=TimingSimpleCPU, num_cpus=1, checker=False, + cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1, + checker=False, mem_size=None): """Initialize a simple base system. @@ -74,11 +75,13 @@ class BaseSystem(object): self.mem_class = mem_class self.cpu_class = cpu_class self.num_cpus = num_cpus + self.num_threads = num_threads self.checker = checker def create_cpus(self, cpu_clk_domain): """Return a list of CPU objects to add to a system.""" - cpus = [ self.cpu_class(clk_domain = cpu_clk_domain, + cpus = [ self.cpu_class(clk_domain=cpu_clk_domain, + numThreads=self.num_threads, cpu_id=i) for i in range(self.num_cpus) ] if self.checker: @@ -187,7 +190,8 @@ class BaseSESystem(BaseSystem): def create_system(self): system = System(physmem = self.mem_class(), membus = SystemXBar(), - mem_mode = self.mem_mode) + mem_mode = self.mem_mode, + multi_thread = (self.num_threads > 1)) system.system_port = system.membus.slave system.physmem.port = system.membus.master self.init_system(system) |