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authorAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:14 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-05-30 12:54:14 -0400
commit3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (patch)
tree309adeb0381c44177d4992a79a5590ba90f61a7e /tests/configs/inorder-timing.py
parent83d99aebb1dcbe015e752fd74e9cd5c6b5ea0380 (diff)
downloadgem5-3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b.tar.xz
mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations to better reflect what memory they are based on. The speed and interface width is now part of the name, and also the alias that is used to select them on the command line. Some minor changes are done to the actual parameters, to better reflect the named configurations. As a result of these changes the regressions change slightly and the stats will be bumped in a separate patch.
Diffstat (limited to 'tests/configs/inorder-timing.py')
-rw-r--r--tests/configs/inorder-timing.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 77c4f3d18..b19014328 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -39,7 +39,7 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleDDR3(),
+ physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave