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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-11 10:23:28 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-11 10:23:28 -0500 |
| commit | 6563ec863444ecd0191d4a3f015b78b06e2906a4 (patch) | |
| tree | 0b5c6c8803d3d590b5330281885cfb3ba0ec97f2 /tests/configs/memtest-filter.py | |
| parent | 550c31849024a2184887df87aae39617ebfe0d6a (diff) | |
| download | gem5-6563ec863444ecd0191d4a3f015b78b06e2906a4.tar.xz | |
cpu: Tidy up the MemTest and make false sharing more obvious
The MemTest class really only tests false sharing, and as such there
was a lot of old cruft that could be removed. This patch cleans up the
tester, and also makes it more clear what the assumptions are. As part
of this simplification the reference functional memory is also
removed.
The regression configs using MemTest are updated to reflect the
changes, and the stats will be bumped in a separate patch. The example
config will be updated in a separate patch due to more extensive
re-work.
In a follow-on patch a new tester will be introduced that uses the
MemChecker to implement true sharing.
Diffstat (limited to 'tests/configs/memtest-filter.py')
| -rw-r--r-- | tests/configs/memtest-filter.py | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py index 35d64a793..42dd05639 100644 --- a/tests/configs/memtest-filter.py +++ b/tests/configs/memtest-filter.py @@ -36,8 +36,7 @@ nb_cores = 8 cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated -system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentXBar(), +system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentXBar(width=16, snoop_filter = SnoopFilter())) # Dummy voltage domain for all our clock domains @@ -63,15 +62,11 @@ for cpu in cpus: # All cpus are associated with cpu_clk_domain cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) - cpu.l1c.cpu_side = cpu.test + cpu.l1c.cpu_side = cpu.port cpu.l1c.mem_side = system.toL2Bus.slave - system.funcbus.slave = cpu.functional system.system_port = system.membus.slave -# connect reference memory to funcbus -system.funcmem.port = system.funcbus.master - # connect memory to membus system.physmem.port = system.membus.master @@ -82,6 +77,3 @@ system.physmem.port = system.membus.master root = Root( full_system = False, system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="Cache CachePort MemoryAccess" -#root.trace.cycle=1 - |