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authorAndreas Hansson <andreas.hansson@arm.com>2014-09-20 17:18:32 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-09-20 17:18:32 -0400
commit1f6d5f8f849f50a3646f586b1274708537124ef3 (patch)
tree03c98c46d500fbd9ac8135baea399813ea3d5644 /tests/configs/memtest-ruby.py
parent1884bcc03ba2b6e734b4bd379d8542596e6d5c84 (diff)
downloadgem5-1f6d5f8f849f50a3646f586b1274708537124ef3.tar.xz
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
Diffstat (limited to 'tests/configs/memtest-ruby.py')
-rw-r--r--tests/configs/memtest-ruby.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 071f3a7b5..08b73cd2f 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -81,7 +81,7 @@ options.num_cpus = nb_cores
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
physmem = SimpleMemory(null = True),
- funcbus = NoncoherentBus())
+ funcbus = NoncoherentXBar())
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain()
system.clk_domain = SrcClockDomain(clock = '1GHz',