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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:40 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:40 -0800 |
| commit | ab2f864af2fd38cbf141708550409f3ca72c675f (patch) | |
| tree | 75b861a290240275d872a58d393a6d6f7e5598d5 /tests/configs/memtest-ruby.py | |
| parent | ceae8383ffeebdc2c12d9a383941c62653471de1 (diff) | |
| download | gem5-ab2f864af2fd38cbf141708550409f3ca72c675f.tar.xz | |
m5: Regression Tester Update
This patch includes the necessary regression updates to test the new ruby
configuration system. The patch includes support for multiple ruby protocols
and adds the ruby random tester. The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses. These tests can be
added back in when ruby supports atomic mode for real.
--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
Diffstat (limited to 'tests/configs/memtest-ruby.py')
| -rw-r--r-- | tests/configs/memtest-ruby.py | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index dd402498e..c34eefe5e 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -1,4 +1,5 @@ # Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2010 Advanced Micro Devices, Inc. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -63,7 +64,11 @@ execfile(os.path.join(config_root, "configs/common", "Options.py")) #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest() for i in xrange(nb_cores) ] + +# ruby does not support atomic, functional, or uncacheable accesses +cpus = [ MemTest(atomic=False, percent_functional=0, \ + percent_uncacheable=0) \ + for i in xrange(nb_cores) ] # overwrite options.num_cpus with the nb_cores value options.num_cpus = nb_cores @@ -91,3 +96,6 @@ for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports): root = Root(system = system) root.system.mem_mode = 'timing' + +# Not much point in this being higher than the L1 latency +m5.ticks.setGlobalFrequency('1ns') |