diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-13 04:48:42 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-05-13 04:48:42 -0400 |
commit | 404a91265efbf1a039fe1e19a8c1d8ff86a904b1 (patch) | |
tree | 3d4c5f1d882fa0c521acf273e8d00fd2a3abdd46 /tests/configs/memtest.py | |
parent | 376cff64bd3ac5bafd8fa566674964fd4836790c (diff) | |
parent | 011db5c8515804145202373440bad26fa21b30a7 (diff) | |
download | gem5-404a91265efbf1a039fe1e19a8c1d8ff86a904b1.tar.xz |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/tmp/newmem
--HG--
extra : convert_revision : 162876cb1ad96ca7ca6a2e0f549c98b29e5a8d2d
Diffstat (limited to 'tests/configs/memtest.py')
-rw-r--r-- | tests/configs/memtest.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f56edef4a..15a4f8f05 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 |