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author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-20 16:39:47 -0400 |
commit | 0b5cf4ba6eb2702ade2bc77c07842edd97eab264 (patch) | |
tree | 4e1ed8130794049e771759059269e6dc23848180 /tests/configs/memtest.py | |
parent | 76c07ea46bc4f8f6d500f909abfb07addf217940 (diff) | |
parent | 6c6b78126a38cf92eef89f027312e1c7a063bd18 (diff) | |
download | gem5-0b5cf4ba6eb2702ade2bc77c07842edd97eab264.tar.xz |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
Diffstat (limited to 'tests/configs/memtest.py')
-rw-r--r-- | tests/configs/memtest.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 116e71af6..2b990418c 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -53,7 +53,7 @@ class L2(BaseCache): #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ] +cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), @@ -90,6 +90,6 @@ system.physmem.port = system.membus.port root = Root( system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="Cache CachePort Bus" -#root.trace.cycle=3810800 +#root.trace.flags="Cache CachePort MemoryAccess" +#root.trace.cycle=1 |