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author | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-03-09 09:59:28 -0500 |
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committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-03-09 09:59:28 -0500 |
commit | da0d67c3d6468bedae93d14a9b7461e2b9d7a645 (patch) | |
tree | cc450e9463d24939d2482b8135f7473c5d15acc2 /tests/configs/o3-timing-checker.py | |
parent | 98cf57fb89b76a8ca423083d52cc647c7923fe51 (diff) | |
download | gem5-da0d67c3d6468bedae93d14a9b7461e2b9d7a645.tar.xz |
CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
Diffstat (limited to 'tests/configs/o3-timing-checker.py')
-rw-r--r-- | tests/configs/o3-timing-checker.py | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py new file mode 100644 index 000000000..dd68a39d7 --- /dev/null +++ b/tests/configs/o3-timing-checker.py @@ -0,0 +1,68 @@ +# Copyright (c) 2011 ARM Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Geoffrey Blake + +import m5 +from m5.objects import * +m5.util.addToPath('../configs/common') + +class MyCache(BaseCache): + assoc = 2 + block_size = 64 + latency = '1ns' + mshrs = 10 + tgts_per_mshr = 5 + +class MyL1Cache(MyCache): + is_top_level = True + tgts_per_mshr = 20 + +cpu = DerivO3CPU(cpu_id=0) +cpu.createInterruptController() +cpu.addCheckerCpu() +cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), + MyL1Cache(size = '256kB'), + MyCache(size = '2MB')) +cpu.clock = '2GHz' + +system = System(cpu = cpu, + physmem = PhysicalMemory(), + membus = Bus()) +system.system_port = system.membus.slave +system.physmem.port = system.membus.master +cpu.connectAllPorts(system.membus) + +root = Root(full_system = False, system = system) |