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authorSteve Reinhardt <steve.reinhardt@amd.com>2009-05-11 10:38:46 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2009-05-11 10:38:46 -0700
commit6df61e1f2409e336dc4ae68eaeae7d0638e65a9d (patch)
tree2de77fed10627294c4d2a1ed18d3e690a9552b14 /tests/configs/o3-timing-mp-ruby.py
parent93f2f69657d0a2420a2c86b71505e6d27e6e2a38 (diff)
downloadgem5-6df61e1f2409e336dc4ae68eaeae7d0638e65a9d.tar.xz
ruby: Set up Ruby regression tests.
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+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.AddToPath('../configs/common')
+
+nb_cores = 4
+cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus, physmem = RubyMemory(num_cpus=nb_cores),
+ membus = Bus())
+
+for cpu in cpus:
+ cpu.connectMemPorts(system.membus)
+ cpu.clock = '2GHz'
+
+# connect memory to membus
+system.physmem.port = system.membus.port
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root(system = system)
+root.system.mem_mode = 'timing'