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authorAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:33 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:33 -0500
commit90bd20aae2bc940397628a4598b5b25f2c8549b5 (patch)
tree27c6eee6bc5609d191ada2ae1a3b30cf9d5d8950 /tests/configs/o3-timing-mp.py
parentf32f372455c99bf5765f5fda3efc7da180dfcda8 (diff)
downloadgem5-90bd20aae2bc940397628a4598b5b25f2c8549b5.tar.xz
tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which worked as long as we never attempted to switch CPUs or checked that a CPU was in a memory system with the correct mode. Future changes will make CPUs verify that they're operating in the correct mode and thus we need to always set it.
Diffstat (limited to 'tests/configs/o3-timing-mp.py')
-rw-r--r--tests/configs/o3-timing-mp.py5
1 files changed, 4 insertions, 1 deletions
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 6f3bddc6f..c3a4929bb 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -35,7 +35,10 @@ nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
+system = System(cpu = cpus,
+ physmem = SimpleDRAM(),
+ membus = CoherentBus(),
+ mem_mode = "timing")
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')