MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.

1 files changed, 4 insertions, 4 deletions

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 95323c2f6..1974d686f 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -62,10 +62,10 @@ Bus())
 # l2cache & bus
 system.toL2Bus = Bus()
 system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
@@ -76,10 +76,10 @@ for cpu in cpus:
     cpu.clock = '2GHz'
 
 # connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
 
 # connect system port to membus
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
 
 # -----------------------
 # run simulation