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| author | Kevin Lim <ktlim@umich.edu> | 2007-03-23 11:22:43 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2007-03-23 11:22:43 -0400 |
| commit | 55a45d364421e50300d64ac02b4d09d975a39eff (patch) | |
| tree | 90346a5025e3bd74c36b664f489867bd683a5f2f /tests/configs/o3-timing.py | |
| parent | fdaff2b1088446325dcb3c270b350b3314dca99a (diff) | |
| download | gem5-55a45d364421e50300d64ac02b4d09d975a39eff.tar.xz | |
A couple of minor fixes.
1. Set CPU ID in all modes for the O3 CPU.
2. Use nextCycle() function to prevent phase drift in O3 CPU.
3. Remove assertion in rename map that is no longer true.
src/cpu/o3/alpha/cpu_builder.cc:
Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident.
src/cpu/o3/alpha/cpu_impl.hh:
Set the CPU ID properly.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces.
src/cpu/o3/rename_map.cc:
Remove assertion that is no longer true.
tests/configs/o3-timing.py:
Set CPU's id to 0.
--HG--
extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
Diffstat (limited to 'tests/configs/o3-timing.py')
| -rw-r--r-- | tests/configs/o3-timing.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index a66cd436e..5600d9f22 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -37,7 +37,7 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 -cpu = DerivO3CPU() +cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) |