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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
| commit | 6daf44dae6dbe931e2a1493cd0e33ca9732509dd (patch) | |
| tree | f8815e56c08a92059b5d576728f564c7bfce7bf0 /tests/configs/o3-timing.py | |
| parent | c4de6a05229bbc42ae4b247541c823edb8d4ca76 (diff) | |
| parent | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (diff) | |
| download | gem5-6daf44dae6dbe931e2a1493cd0e33ca9732509dd.tar.xz | |
Automated merge with ssh://hg@repo.m5sim.org/m5
Diffstat (limited to 'tests/configs/o3-timing.py')
| -rw-r--r-- | tests/configs/o3-timing.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index a4c054122..d4a69d94a 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -37,8 +37,12 @@ class MyCache(BaseCache): mshrs = 10 tgts_per_mshr = 5 +class MyL1Cache(MyCache): + is_top_level = True + cpu = DerivO3CPU(cpu_id=0) -cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), +cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'), + MyL1Cache(size = '256kB'), MyCache(size = '2MB')) cpu.clock = '2GHz' |