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authorWendy Elsasser <wendy.elsasser@arm.com>2017-02-14 15:09:18 -0600
committerWendy Elsasser <wendy.elsasser@arm.com>2017-02-14 15:09:18 -0600
commitca0fd665dcf6a4aeda07955d3898b03204c88fd8 (patch)
tree5c508419acd3e09ba46a595fe8fe8363ed9d11de /tests/configs/o3-timing.py
parent94e612665020d49e6cba659536e315be8ef1c71e (diff)
downloadgem5-ca0fd665dcf6a4aeda07955d3898b03204c88fd8.tar.xz
mem: Update DRAM configuration names
Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH> The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Diffstat (limited to 'tests/configs/o3-timing.py')
-rw-r--r--tests/configs/o3-timing.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index c573277d1..050e4050e 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -48,8 +48,8 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
- root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()
else:
- root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()