MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.

1 files changed, 2 insertions, 2 deletions

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 9701b1012..3003f0bcd 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -50,8 +50,8 @@ cpu.clock = '2GHz'
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
-system.system_port = system.membus.port
-system.physmem.port = system.membus.port
+system.system_port = system.membus.slave
+system.physmem.port = system.membus.master
 cpu.connectAllPorts(system.membus)
 
 root = Root(full_system = False, system = system)