summaryrefslogtreecommitdiff
path: root/tests/configs/pc-o3-timing.py
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:07:09 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-10-15 08:07:09 -0400
commit3cf733bcc07b0a8bf069f8581b7f3902bc38f0e0 (patch)
tree8513d98d2e8d19c0742084a5fa2f9e9930aa1367 /tests/configs/pc-o3-timing.py
parent930db9257dbac7e678888a65a17c39bcc87aa7fa (diff)
downloadgem5-3cf733bcc07b0a8bf069f8581b7f3902bc38f0e0.tar.xz
Regression: Use addTwoLevelCacheHierarchy in configs
This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween. The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock. The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache.
Diffstat (limited to 'tests/configs/pc-o3-timing.py')
-rw-r--r--tests/configs/pc-o3-timing.py29
1 files changed, 13 insertions, 16 deletions
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index c3e705705..f75c5776d 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -90,28 +90,25 @@ cpu = DerivO3CPU(cpu_id=0)
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
-system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
+#create the iocache
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- PageTableWalkerCache(),
- PageTableWalkerCache())
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8),
+ PageTableWalkerCache(),
+ PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)