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authorAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:24:37 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:24:37 -0500
commit6daf44dae6dbe931e2a1493cd0e33ca9732509dd (patch)
treef8815e56c08a92059b5d576728f564c7bfce7bf0 /tests/configs/pc-simple-atomic.py
parentc4de6a05229bbc42ae4b247541c823edb8d4ca76 (diff)
parent63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (diff)
downloadgem5-6daf44dae6dbe931e2a1493cd0e33ca9732509dd.tar.xz
Automated merge with ssh://hg@repo.m5sim.org/m5
Diffstat (limited to 'tests/configs/pc-simple-atomic.py')
-rw-r--r--tests/configs/pc-simple-atomic.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 382899eb5..1c35ff2d9 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -43,6 +43,7 @@ class L1(BaseCache):
block_size = 64
mshrs = 4
tgts_per_mshr = 8
+ is_top_level = True
# ----------------------
# Base L2 Cache
@@ -65,6 +66,7 @@ class PageTableWalkerCache(BaseCache):
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
+ is_top_level = True
# ---------------------
# I/O Cache
@@ -78,6 +80,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
addr_range = AddrRange(0, size=mem_size)
forward_snoops = False
+ is_top_level = True
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)