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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
commit | 95a0b184314cf0171a20fb7e71c845891dc56496 (patch) | |
tree | 00590e68aa9d66c225a8f0d08f82eca2771e461d /tests/configs/pc-simple-timing-ruby.py | |
parent | 8ccfd9defa930d5c2904134d7a7286682e721db9 (diff) | |
download | gem5-95a0b184314cf0171a20fb7e71c845891dc56496.tar.xz |
ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out. All the memory accesses now source and sink values
to the memory maintained by ruby.
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
-rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 2ac571c83..633a19e2f 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -68,12 +68,16 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) for i in xrange(options.num_cpus)] -Ruby.create_system(options, system, system.iobus, system._dma_ports) +Ruby.create_system(options, True, system, system.iobus, system._dma_ports) # Create a seperate clock domain for Ruby system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = system.voltage_domain) +# Connect the ruby io port to the PIO bus, +# assuming that there is just one such port. +system.iobus.master = system.ruby._io_port.slave + for (i, cpu) in enumerate(system.cpu): # create the interrupt controller cpu.createInterruptController() @@ -82,17 +86,13 @@ for (i, cpu) in enumerate(system.cpu): cpu.dcache_port = system.ruby._cpu_ports[i].slave cpu.itb.walker.port = system.ruby._cpu_ports[i].slave cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave + cpu.interrupts.pio = system.ruby._cpu_ports[i].master cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master - # Set access_phys_mem to True for ruby port - system.ruby._cpu_ports[i].access_phys_mem = True - -system.physmem = [DDR3_1600_x64(range = r) +system.physmem = [SimpleMemory(range = r, null = True) for r in system.mem_ranges] -for i in xrange(len(system.physmem)): - system.physmem[i].port = system.iobus.master root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') |