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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:33 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:33 -0400 |
| commit | 49d88f08b0ff463bca04285dca240b3730889a1d (patch) | |
| tree | e4affba86713db0136091f1c9c25ff6e975048a9 /tests/configs/pc-simple-timing-ruby.py | |
| parent | e553844efc4247f5be870fad5ea919af85858a55 (diff) | |
| download | gem5-49d88f08b0ff463bca04285dca240b3730889a1d.tar.xz | |
mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
| -rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index fcbfd6b7f..57f9b6679 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -89,8 +89,7 @@ for (i, cpu) in enumerate(system.cpu): # Set access_phys_mem to True for ruby port system.ruby._cpu_ruby_ports[i].access_phys_mem = True -system.physmem = [DDR3_1600_x64(range = r, - conf_table_reported = True) +system.physmem = [DDR3_1600_x64(range = r) for r in system.mem_ranges] for i in xrange(len(system.physmem)): system.physmem[i].port = system.piobus.master |