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authorNilay Vaish <nilay@cs.wisc.edu>2014-03-20 08:03:09 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-03-20 08:03:09 -0500
commitd5b5d89b34da1cd311974bffd3834bff451efe0e (patch)
treec57076b3bb1513fad91edacea018a75f5737efd3 /tests/configs/pc-simple-timing-ruby.py
parent9b3418d163ea2225a9d652b923333b04733a1e0b (diff)
downloadgem5-d5b5d89b34da1cd311974bffd3834bff451efe0e.tar.xz
config: remove ruby_fs.py
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression.
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
-rw-r--r--tests/configs/pc-simple-timing-ruby.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 81ec2fa9b..3d1b78324 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -68,7 +68,7 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
for i in xrange(options.num_cpus)]
-Ruby.create_system(options, system, system.piobus, system._dma_ports)
+Ruby.create_system(options, system, system.iobus, system._dma_ports)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
@@ -92,7 +92,7 @@ for (i, cpu) in enumerate(system.cpu):
system.physmem = [DDR3_1600_x64(range = r)
for r in system.mem_ranges]
for i in xrange(len(system.physmem)):
- system.physmem[i].port = system.piobus.master
+ system.physmem[i].port = system.iobus.master
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')