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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /tests/configs/pc-simple-timing-ruby.py | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
| -rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 782cda60d..006aeb6a4 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -87,9 +87,9 @@ for (i, cpu) in enumerate(system.cpu): cpu.itb.walker.port = system.ruby._cpu_ports[i].slave cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave - cpu.interrupts.pio = system.ruby._cpu_ports[i].master - cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave - cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master + cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master + cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave + cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') |