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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-06 21:53:57 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-06 21:53:57 -0600 |
| commit | c0618198908b592ff0c165b671cb5d8d785d83ca (patch) | |
| tree | 96b98dbf6262a9f417c7d53ef59c09ff56018e2c /tests/configs/pc-simple-timing-ruby.py | |
| parent | e8802fa127f5a446e708eb9f7ce8509e850bf699 (diff) | |
| download | gem5-c0618198908b592ff0c165b671cb5d8d785d83ca.tar.xz | |
ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
| -rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 0753472bc..23a0bb3d0 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -74,5 +74,8 @@ for (i, cpu) in enumerate(system.cpu): cpu.interrupts.int_slave = system.piobus.master cpu.clock = '2GHz' + # Set access_phys_mem to True for ruby port + system.ruby._cpu_ruby_ports[i].access_phys_mem = True + root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') |