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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-03-17 19:24:37 -0500 |
| commit | 6daf44dae6dbe931e2a1493cd0e33ca9732509dd (patch) | |
| tree | f8815e56c08a92059b5d576728f564c7bfce7bf0 /tests/configs/pc-simple-timing.py | |
| parent | c4de6a05229bbc42ae4b247541c823edb8d4ca76 (diff) | |
| parent | 63eb337b3b93ab71ab3157ec6487901d4fc6cda6 (diff) | |
| download | gem5-6daf44dae6dbe931e2a1493cd0e33ca9732509dd.tar.xz | |
Automated merge with ssh://hg@repo.m5sim.org/m5
Diffstat (limited to 'tests/configs/pc-simple-timing.py')
| -rw-r--r-- | tests/configs/pc-simple-timing.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index 7452e2542..9c9f4aeca 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -44,6 +44,7 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 + is_top_level = True # ---------------------- # Base L2 Cache |