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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-09 09:59:25 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-09 09:59:25 -0500 |
| commit | eaa994e7f6c12f6dc3e17836052f76a5ce9bdc01 (patch) | |
| tree | d24450f54631a6e82b3c01b93fcf9e698eeee708 /tests/configs/pc-simple-timing.py | |
| parent | cda4c2d280e9c1becf3b4d0b6b384f63641c45ba (diff) | |
| download | gem5-eaa994e7f6c12f6dc3e17836052f76a5ce9bdc01.tar.xz | |
cache: Allow main memory to be at disjoint address ranges.
Diffstat (limited to 'tests/configs/pc-simple-timing.py')
| -rw-r--r-- | tests/configs/pc-simple-timing.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index b5117f2fe..fbe6b4c4f 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -78,7 +78,7 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 - addr_range = AddrRange(0, size=mem_size) + addr_ranges = [AddrRange(0, size=mem_size)] forward_snoops = False #cpu @@ -91,7 +91,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() -system.iocache = IOCache(addr_range=mem_size) +system.iocache = IOCache() system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave |