tests: Create base classes to encapsulate common test configurations

Most of the test cases currently contain a large amount of duplicated
boiler plate code. This changeset introduces a set of classes that
encapsulates most of the functionality when setting up a test
configuration.

The following base classes are introduced:
* BaseSystem - Basic system configuration that can be used for both
               SE and FS simulation.

* BaseFSSystem - Basic FS configuration uni-processor and multi-processor
                 configurations.

* BaseFSSystemUniprocessor - Basic FS configuration for uni-processor
                             configurations. This is provided as a way
			     to make existing test cases backwards
			     compatible.

Architecture specific implementations are provided for ARM, Alpha, and
X86.

1 files changed, 7 insertions, 35 deletions

diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index 8c5d4086d..3f252bf2c 100644
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -1,5 +1,5 @@
-# Copyright (c) 2011 ARM Limited
-# All rights reserved
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
 # not be construed as granting a license to any other intellectual
@@ -33,39 +33,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Geoffrey Blake
+# Authors: Andreas Sandberg
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-import FSConfig
-from Caches import *
-
-#cpu
-cpu = DerivO3CPU(cpu_id=0)
-#the system
-system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
-
-system.cpu = cpu
-#connect up the checker
-cpu.addCheckerCpu()
-
-#create the iocache
-system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
-system.iocache.cpu_side = system.iobus.master
-system.iocache.mem_side = system.membus.slave
-
-#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
-                              L1Cache(size = '32kB', assoc = 4),
-                              L2Cache(size = '4MB', assoc = 8))
-# create the interrupt controller
-cpu.createInterruptController()
-# connect cpu and caches to the rest of the system
-cpu.connectAllPorts(system.membus)
-# set the cpu clock along with the caches and l1-l2 bus
-cpu.clock = '2GHz'
-
-root = Root(full_system=True, system=system)
-m5.ticks.setGlobalFrequency('1THz')
+from arm_generic import *
 
+root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+                                    cpu_class=DerivO3CPU,
+                                    checker=True).create_root()