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authorMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-09-25 11:49:41 -0500
committerMrinmoy Ghosh <mrinmoy.ghosh@arm.com>2012-09-25 11:49:41 -0500
commit6fc0094337bc0356c55232c3850fb5fd2dab1f0c (patch)
treef23261eb3f3a7e91b08505e68015941b1d04ba7c /tests/configs/realview-o3-dual.py
parent74ab69c7eafc2f0d187ce3ba7d6b9a59ba291b9f (diff)
downloadgem5-6fc0094337bc0356c55232c3850fb5fd2dab1f0c.tar.xz
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path.
Diffstat (limited to 'tests/configs/realview-o3-dual.py')
-rw-r--r--tests/configs/realview-o3-dual.py9
1 files changed, 6 insertions, 3 deletions
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index e6ca2d7bd..aa756c07f 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -37,7 +37,8 @@ from Benchmarks import *
# ====================
class L1(BaseCache):
- latency = '1ns'
+ hit_latency = '1ns'
+ response_latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 20
@@ -49,7 +50,8 @@ class L1(BaseCache):
class L2(BaseCache):
block_size = 64
- latency = '10ns'
+ hit_latency = '10ns'
+ response_latency = '10ns'
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
@@ -60,7 +62,8 @@ class L2(BaseCache):
class IOCache(BaseCache):
assoc = 8
block_size = 64
- latency = '50ns'
+ hit_latency = '50ns'
+ response_latency = '50ns'
mshrs = 20
size = '1kB'
tgts_per_mshr = 12