diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-03-02 09:21:48 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-03-02 09:21:48 -0500 |
| commit | 32eae8094d8931f161784825ad013e9c6d995c17 (patch) | |
| tree | ef3dc2b37cecd53d7bd1fcd5809b0ed251f30b3a /tests/configs/realview-o3.py | |
| parent | c0b9f324bf2780b344bef04a4ce7ee063e172e40 (diff) | |
| download | gem5-32eae8094d8931f161784825ad013e9c6d995c17.tar.xz | |
CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.
The patch also adds the "createInterruptController" call to a number
of the regression scripts.
Diffstat (limited to 'tests/configs/realview-o3.py')
| -rw-r--r-- | tests/configs/realview-o3.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 058111d67..795bd534a 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) +# create the interrupt controller +cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' |