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author | Chander Sudanthi <chander.sudanthi@arm.com> | 2011-12-01 00:15:22 -0800 |
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committer | Chander Sudanthi <chander.sudanthi@arm.com> | 2011-12-01 00:15:22 -0800 |
commit | 61c14da751ae80e8c19e0b63ddd629c4152f1c72 (patch) | |
tree | a1c74b7afe115082c4ca5a5f1797d3de14772041 /tests/configs/realview-o3.py | |
parent | fa753c14549a768f0b8475e4e183acbdc394c248 (diff) | |
download | gem5-61c14da751ae80e8c19e0b63ddd629c4152f1c72.tar.xz |
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.
--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
Diffstat (limited to 'tests/configs/realview-o3.py')
-rw-r--r-- | tests/configs/realview-o3.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py index 89f320c04..61e7591e6 100644 --- a/tests/configs/realview-o3.py +++ b/tests/configs/realview-o3.py @@ -40,7 +40,7 @@ class L1(BaseCache): latency = '1ns' block_size = 64 mshrs = 4 - tgts_per_mshr = 8 + tgts_per_mshr = 20 is_top_level = True # ---------------------- |