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authorAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:09 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:09 -0500
commitba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe (patch)
tree5cf148fb600af2da5440a442d10170666ae8bbc9 /tests/configs/realview-o3.py
parentc9d5985b8221459e4737c637910dc08513b05660 (diff)
downloadgem5-ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe.tar.xz
ARM: Add some MP regressions and clean up the disk images and kernels a bit
Diffstat (limited to 'tests/configs/realview-o3.py')
-rw-r--r--tests/configs/realview-o3.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index 2d805fe0a..89f320c04 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -64,7 +64,7 @@ class IOCache(BaseCache):
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
- addr_range=AddrRange(0, size='128MB')
+ addr_range=AddrRange(0, size='256MB')
forward_snoops = False
#cpu
@@ -76,7 +76,7 @@ system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
-system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')]
+system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')]
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.port
system.iocache.mem_side = system.membus.port