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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-26 06:42:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-26 06:42:42 -0400 |
| commit | 651de2d9af8ac628b69b40812ff036231da40ae3 (patch) | |
| tree | abb19706695f402c23370963ecd20166f657681d /tests/configs/realview-simple-atomic.py | |
| parent | b387d8e2136b6eccf590e5223096dce6830a66ec (diff) | |
| download | gem5-651de2d9af8ac628b69b40812ff036231da40ae3.tar.xz | |
config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
Diffstat (limited to 'tests/configs/realview-simple-atomic.py')
| -rw-r--r-- | tests/configs/realview-simple-atomic.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index 2d1efe3fe..5cad3a2cb 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches -cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4), - L2(size = '4MB', assoc = 8)) +cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4), + L2Cache(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() # connect cpu and caches to the rest of the system |