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author | Dam Sunwoo <dam.sunwoo@arm.com> | 2012-02-12 16:07:39 -0600 |
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committer | Dam Sunwoo <dam.sunwoo@arm.com> | 2012-02-12 16:07:39 -0600 |
commit | 230540e655efd09ad057e7fde2ac257f355c06d1 (patch) | |
tree | 4555eeff33db9ac5c2f3a1b210627cef4b81d4ad /tests/configs/realview-simple-timing-dual.py | |
parent | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (diff) | |
download | gem5-230540e655efd09ad057e7fde2ac257f355c06d1.tar.xz |
mem: fix cache stats to use request ids correctly
This patch fixes the cache stats to use the new request ids.
Cache stats also display the requestor names in the vector subnames.
Most cache stats now include "nozero" and "nonan" flags to reduce the
amount of excessive cache stat dump. Also, simplified
incMissCount()/incHitCount() functions.
Diffstat (limited to 'tests/configs/realview-simple-timing-dual.py')
-rw-r--r-- | tests/configs/realview-simple-timing-dual.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 81646f825..95daa81b6 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -83,7 +83,6 @@ system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port system.l2c.mem_side = system.membus.port -system.l2c.num_cpus = 2 #connect up the cpu and l1s for c in cpus: |