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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-08-19 15:08:09 -0500 |
| commit | ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe (patch) | |
| tree | 5cf148fb600af2da5440a442d10170666ae8bbc9 /tests/configs/realview-simple-timing.py | |
| parent | c9d5985b8221459e4737c637910dc08513b05660 (diff) | |
| download | gem5-ba265abbfd70060cc61a3b4a53b4b1cfcb7a96fe.tar.xz | |
ARM: Add some MP regressions and clean up the disk images and kernels a bit
Diffstat (limited to 'tests/configs/realview-simple-timing.py')
| -rw-r--r-- | tests/configs/realview-simple-timing.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py index 83b643c52..74fc617f3 100644 --- a/tests/configs/realview-simple-timing.py +++ b/tests/configs/realview-simple-timing.py @@ -64,7 +64,7 @@ class IOCache(BaseCache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 - addr_range=AddrRange(0, size='128MB') + addr_range=AddrRange(0, size='256MB') forward_snoops = False #cpu @@ -76,7 +76,7 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] -system.bridge.filter_ranges_b=[AddrRange(0, size='128MB')] +system.bridge.filter_ranges_b=[AddrRange(0, size='256MB')] system.iocache = IOCache() system.iocache.cpu_side = system.iobus.port system.iocache.mem_side = system.membus.port |