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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-03 20:23:00 -0800 |
| commit | 00f24ae92c7b9aa73e12fd8160b5756e80126db2 (patch) | |
| tree | 1d149846db0efdc77c635891c6c1433d3af1817d /tests/configs/simple-atomic-mp-ruby.py | |
| parent | 869a046e413d7cbfdda4e33eed8191004017a83f (diff) | |
| download | gem5-00f24ae92c7b9aa73e12fd8160b5756e80126db2.tar.xz | |
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
Diffstat (limited to 'tests/configs/simple-atomic-mp-ruby.py')
| -rw-r--r-- | tests/configs/simple-atomic-mp-ruby.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py index 570a1766a..705f13ef3 100644 --- a/tests/configs/simple-atomic-mp-ruby.py +++ b/tests/configs/simple-atomic-mp-ruby.py @@ -41,7 +41,7 @@ system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) # add L1 caches for cpu in cpus: - cpu.connectMemPorts(system.membus) + cpu.connectAllPorts(system.membus) cpu.clock = '2GHz' # connect memory to membus |