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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-02 04:00:47 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-02 04:00:47 -0500
commit36dc93a5fa09765b9d2bac402bb557d228effcad (patch)
tree3a0899247304a0800653f73f515617027ee8dba0 /tests/configs/simple-atomic-mp-ruby.py
parentd35dd71ab4ac44a79ac22dca82277a43cd59f3c6 (diff)
downloadgem5-36dc93a5fa09765b9d2bac402bb557d228effcad.tar.xz
mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
Diffstat (limited to 'tests/configs/simple-atomic-mp-ruby.py')
-rw-r--r--tests/configs/simple-atomic-mp-ruby.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 321cb977f..bdda6d005 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -38,7 +38,7 @@ import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentXBar(),
+system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
clk_domain = SrcClockDomain(clock = '1GHz'))
# Create a seperate clock domain for components that should run at