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authorKevin Lim <ktlim@umich.edu>2007-04-22 15:31:33 -0400
committerKevin Lim <ktlim@umich.edu>2007-04-22 15:31:33 -0400
commitdbc1edd23deed386c952a77488a70f20485da711 (patch)
tree9b220cc95d94064a5e001b2d65db5b064d8bc7cb /tests/configs/simple-atomic-mp.py
parent088a0565836fc678fabef3c8662de79595bf20c2 (diff)
parent67a37e83f3b69f832ae05c4612979c2c31bb4d3e (diff)
downloadgem5-dbc1edd23deed386c952a77488a70f20485da711.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head --HG-- extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
Diffstat (limited to 'tests/configs/simple-atomic-mp.py')
-rw-r--r--tests/configs/simple-atomic-mp.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index f9e4e2767..e8000cd0a 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@ for cpu in cpus:
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
+ cpu.clock = '2GHz'
# connect memory to membus
system.physmem.port = system.membus.port