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| author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-25 11:53:06 -0600 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-25 11:53:06 -0600 |
| commit | cf08b232ffeb3cb9bfd10f999ae5562ce1528034 (patch) | |
| tree | 26bc20dc524abba5721f992fcd9f51bbea82bb6b /tests/configs/simple-timing-mp-ruby.py | |
| parent | 5b90934dd20d4ed5f5d4f439ccded7417d328e9b (diff) | |
| parent | 5a4ebd6d1293b51cadc33d5556daff81fd76799a (diff) | |
| download | gem5-cf08b232ffeb3cb9bfd10f999ae5562ce1528034.tar.xz | |
Automated merge with ssh://hg@m5sim.org/m5
Diffstat (limited to 'tests/configs/simple-timing-mp-ruby.py')
| -rw-r--r-- | tests/configs/simple-timing-mp-ruby.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py index ed4b5b4c6..416983014 100644 --- a/tests/configs/simple-timing-mp-ruby.py +++ b/tests/configs/simple-timing-mp-ruby.py @@ -33,7 +33,7 @@ nb_cores = 4 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] import ruby_config -ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores) +ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) # system simulated system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) |