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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 19:00:59 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 19:00:59 -0500 |
| commit | b565660c42cbf8f9ec9442cd6c0b7d488c7816af (patch) | |
| tree | aa977395b10e164190efdd5106da54a57bc23b44 /tests/configs/simple-timing-mp.py | |
| parent | 8dbab9f701150cf93d33f2a21d6b556507f3d617 (diff) | |
| parent | 9ef8bf74c7ab3d34889e804cb4b1e365da090d0b (diff) | |
| download | gem5-b565660c42cbf8f9ec9442cd6c0b7d488c7816af.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem/
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
Diffstat (limited to 'tests/configs/simple-timing-mp.py')
| -rw-r--r-- | tests/configs/simple-timing-mp.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 8f9ab0dde..0d99d8714 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) - cpu.mem = cpu.dcache # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) |