diff options
| author | Kevin Lim <ktlim@umich.edu> | 2006-11-10 12:44:15 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-10 12:44:15 -0500 |
| commit | b5e68fb54677f601bb00c23af52db8fd6571301f (patch) | |
| tree | dc3c17198ba4010d907ecd8cb7189aa7959948d4 /tests/configs/simple-timing-mp.py | |
| parent | 264f9ce374ff4689fec3c32d8289fe76b0b65078 (diff) | |
| parent | 9ef51f2dbaba88c10366d708f0ca872bb39064e4 (diff) | |
| download | gem5-b5e68fb54677f601bb00c23af52db8fd6571301f.tar.xz | |
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
Diffstat (limited to 'tests/configs/simple-timing-mp.py')
| -rw-r--r-- | tests/configs/simple-timing-mp.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 8f9ab0dde..0d99d8714 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -70,7 +70,6 @@ system.l2c.mem_side = system.membus.port for cpu in cpus: cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4)) - cpu.mem = cpu.dcache # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) |