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authorGabe Black <gblack@eecs.umich.edu>2007-04-23 15:34:40 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-23 15:34:40 +0000
commitcca881a5316d686f0be6b437e756a9faba43aa02 (patch)
tree1c46278b51c66879e228b696dee64787fc487704 /tests/configs/simple-timing-mp.py
parentf0929006965514982603fe58ebc3211acf021cce (diff)
parenta006aa067a197f5ce2cd3f22ffe30ae3d9103cbf (diff)
downloadgem5-cca881a5316d686f0be6b437e756a9faba43aa02.tar.xz
Merge zizzer.eecs.umich.edu:/n/wexford/x/gblack/m5/newmem-o3-spec
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro --HG-- extra : convert_revision : 757e1d79033e6f8e0aaaf5ecaf14077d416cff8e
Diffstat (limited to 'tests/configs/simple-timing-mp.py')
-rw-r--r--tests/configs/simple-timing-mp.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 0d99d8714..a263bcf57 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@ for cpu in cpus:
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
+ cpu.clock = '2GHz'
# connect memory to membus
system.physmem.port = system.membus.port