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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-13 06:43:09 -0500 |
commit | 5a9a743cfc4517f93e5c94533efa767b92272c59 (patch) | |
tree | f3dbc078a51e5759b26b1a5f16263ddb1cf55a7b /tests/configs/simple-timing-mp.py | |
parent | 8cb4a2208d568eb86ad3f6c6bb250bcbe2952302 (diff) | |
download | gem5-5a9a743cfc4517f93e5c94533efa767b92272c59.tar.xz |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.
Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
Diffstat (limited to 'tests/configs/simple-timing-mp.py')
-rw-r--r-- | tests/configs/simple-timing-mp.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 06d535154..5ec7a6067 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -61,10 +61,10 @@ Bus()) # l2cache & bus system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port +system.l2c.cpu_side = system.toL2Bus.master # connect l2c to membus -system.l2c.mem_side = system.membus.port +system.l2c.mem_side = system.membus.slave # add L1 caches for cpu in cpus: @@ -74,10 +74,10 @@ for cpu in cpus: cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' -system.system_port = system.membus.port +system.system_port = system.membus.slave # connect memory to membus -system.physmem.port = system.membus.port +system.physmem.port = system.membus.master # ----------------------- |