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authorKevin Lim <ktlim@umich.edu>2007-04-22 14:39:39 -0400
committerKevin Lim <ktlim@umich.edu>2007-04-22 14:39:39 -0400
commitd1f9414e111b4b5e6d0f60ca64a415a47765e9e0 (patch)
tree1bb6a06cffe906558ebf86873236be9e643d88a2 /tests/configs/simple-timing-mp.py
parent25e92383c839f6d69f933f614fd3f9acef907075 (diff)
downloadgem5-d1f9414e111b4b5e6d0f60ca64a415a47765e9e0.tar.xz
Update configs to set the CPU clock properly.
--HG-- extra : convert_revision : 62fec666f987e9a9a441e319458908483cd2c5ff
Diffstat (limited to 'tests/configs/simple-timing-mp.py')
-rw-r--r--tests/configs/simple-timing-mp.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 0d99d8714..a263bcf57 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@ for cpu in cpus:
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
+ cpu.clock = '2GHz'
# connect memory to membus
system.physmem.port = system.membus.port