m5: Regression Tester Update

This patch includes the necessary regression updates to test the new ruby
configuration system.  The patch includes support for multiple ruby protocols
and adds the ruby random tester.  The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses.  These tests can be
added back in when ruby supports atomic mode for real.

--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py

1 files changed, 54 insertions, 7 deletions

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index de63a8bbb..8ca89cdac 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -28,16 +28,63 @@
 
 import m5
 from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+import os, optparse, sys
 
-import ruby_config
-ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
+if buildEnv['FULL_SYSTEM']:
+    panic("This script requires system-emulation mode (*_SE).")
+
+# Get paths we might need
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+addToPath(config_root+'/configs/common')
+addToPath(config_root+'/configs/ruby')
+
+import Ruby
+
+parser = optparse.OptionParser()
+
+#
+# Set the default cache size and associativity to be very small to encourage
+# races between requests and writebacks.
+#
+parser.add_option("--l1d_size", type="string", default="256B")
+parser.add_option("--l1i_size", type="string", default="256B")
+parser.add_option("--l2_size", type="string", default="512B")
+parser.add_option("--l1d_assoc", type="int", default=2)
+parser.add_option("--l1i_assoc", type="int", default=2)
+parser.add_option("--l2_assoc", type="int", default=2)
+
+execfile(os.path.join(config_root, "configs/common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+# this is a uniprocessor only test
+options.num_cpus = 1
 
 cpu = TimingSimpleCPU(cpu_id=0)
 system = System(cpu = cpu,
-                physmem = ruby_memory,
-                membus = Bus())
-system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
-cpu.clock = '2GHz'
+                physmem = PhysicalMemory())
+
+system.ruby = Ruby.create_system(options, system.physmem)
+
+assert(len(system.ruby.cpu_ruby_ports) == 1)
+
+#
+# Tie the cpu cache ports to the ruby cpu ports and
+# physmem, respectively
+#
+cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
+cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
+
+# -----------------------
+# run simulation
+# -----------------------
 
 root = Root(system = system)
+root.system.mem_mode = 'timing'
+
+# Not much point in this being higher than the L1 latency
+m5.ticks.setGlobalFrequency('1ns')