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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 09:14:14 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-03-20 09:14:14 -0500 |
commit | b5cc4c760478240bf8c5f7de977bf2b56fd8dfd4 (patch) | |
tree | f4d9bf0eee60c59b294f8e25504e67e58bfdd1f6 /tests/configs/simple-timing-ruby.py | |
parent | f2059f8399b22ecc544413a0e9d5a13a6f965411 (diff) | |
download | gem5-b5cc4c760478240bf8c5f7de977bf2b56fd8dfd4.tar.xz |
config: ruby: rename _cpu_ruby_ports to _cpu_ports
Diffstat (limited to 'tests/configs/simple-timing-ruby.py')
-rw-r--r-- | tests/configs/simple-timing-ruby.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 94cb15ed4..90af9c920 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -85,7 +85,7 @@ Ruby.create_system(options, system) system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = system.voltage_domain) -assert(len(system.ruby._cpu_ruby_ports) == 1) +assert(len(system.ruby._cpu_ports) == 1) # create the interrupt controller cpu.createInterruptController() @@ -94,7 +94,7 @@ cpu.createInterruptController() # Tie the cpu cache ports to the ruby cpu ports and # physmem, respectively # -cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0]) +cpu.connectAllPorts(system.ruby._cpu_ports[0]) # ----------------------- # run simulation |