Cache: add a response latency to the caches

In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.

1 files changed, 3 insertions, 2 deletions

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 33d03f6cf..cb40ca5c3 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -32,7 +32,8 @@ from m5.objects import *
 class MyCache(BaseCache):
     assoc = 2
     block_size = 64
-    latency = '1ns'
+    hit_latency = '1ns'
+    response_latency = '1ns'
     mshrs = 10
     tgts_per_mshr = 5
 
@@ -42,7 +43,7 @@ class MyL1Cache(MyCache):
 cpu = TimingSimpleCPU(cpu_id=0)
 cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                               MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB', latency='10ns'))
+                              MyCache(size = '2MB', hit_latency='10ns', response_latency ='10ns'))
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
                 membus = CoherentBus())