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authorGabe Black <gblack@eecs.umich.edu>2007-04-23 11:34:39 -0400
committerGabe Black <gblack@eecs.umich.edu>2007-04-23 11:34:39 -0400
commita006aa067a197f5ce2cd3f22ffe30ae3d9103cbf (patch)
tree1a10eafaa85a1f97b17b040813fd6348aa1db9d2 /tests/configs/simple-timing.py
parentf3a0abbecc3456147f1ca3e297a50ae4353316fd (diff)
parentdbc1edd23deed386c952a77488a70f20485da711 (diff)
downloadgem5-a006aa067a197f5ce2cd3f22ffe30ae3d9103cbf.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 12f10c174f0eca1ddf74b672414fbe78251f686b
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r--tests/configs/simple-timing.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index d7d505a5a..6c4b8232f 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -44,5 +44,6 @@ system = System(cpu = cpu,
membus = Bus())
system.physmem.port = system.membus.port
cpu.connectMemPorts(system.membus)
+cpu.clock = '2GHz'
root = Root(system = system)