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authorKevin Lim <ktlim@umich.edu>2006-10-31 14:37:19 -0500
committerKevin Lim <ktlim@umich.edu>2006-10-31 14:37:19 -0500
commit5825a6c9d82b813d983b688da5f1ce18c90f774f (patch)
treea5be1a1c3968ff57d387523f95e46bcb2797c121 /tests/configs/simple-timing.py
parent7f39644609e19ada9e94c9bbb09c3e625fa6e8ed (diff)
parentbfd5eb2b08dad700d085a637d5e16a61dcc530d7 (diff)
downloadgem5-5825a6c9d82b813d983b688da5f1ce18c90f774f.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix configs/example/fs.py: configs/example/se.py: src/mem/tport.hh: Hand merge. --HG-- extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r--tests/configs/simple-timing.py2
1 files changed, 0 insertions, 2 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 60190b47c..d7d505a5a 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,8 +39,6 @@ class MyCache(BaseCache):
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
-cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())