summaryrefslogtreecommitdiff
path: root/tests/configs/simple-timing.py
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-11-01 19:00:59 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-01 19:00:59 -0500
commitb565660c42cbf8f9ec9442cd6c0b7d488c7816af (patch)
treeaa977395b10e164190efdd5106da54a57bc23b44 /tests/configs/simple-timing.py
parent8dbab9f701150cf93d33f2a21d6b556507f3d617 (diff)
parent9ef8bf74c7ab3d34889e804cb4b1e365da090d0b (diff)
downloadgem5-b565660c42cbf8f9ec9442cd6c0b7d488c7816af.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem/
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r--tests/configs/simple-timing.py2
1 files changed, 0 insertions, 2 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 60190b47c..d7d505a5a 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -39,8 +39,6 @@ class MyCache(BaseCache):
cpu = TimingSimpleCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
-cpu.mem = cpu.dcache
system = System(cpu = cpu,
physmem = PhysicalMemory(),
membus = Bus())